The present invention relates to a method of manufacturing a semiconductor integrated circuit and, more particularly, to a method of manufacturing a Bi-CMOS integrated circuit.
In current Bi-CMOS integrated circuits, a structure having n.sup.+ -/p.sup.+ -type buried regions and n-/p-type wells is most widely used.
A conventional technique of forming n.sup.+ -/p.sup.+ -type buried regions in one mask formation step in order to decrease the number of mask formation steps will be described below with reference to FIGS. 2A to 2F.
As shown in FIG. 2A, a first silicon oxide film 2 and a silicon nitride film 3 are formed on a p-type silicon substrate 1.
As shown in FIG. 2B, the silicon nitride film 3 and the first silicon oxide film 2 are partially removed. Thereafter, n.sup.+ -type regions 6a and 6b are selectively formed by solid-phase diffusion of arsenic.
As shown in FIG. 2C, a third silicon oxide film 7 is formed by selective oxidation using the silicon nitride film 3 as a mask.
As shown in FIG. 2D, after the silicon nitride film 3 and the first silicon oxide film 2 are removed, p.sup.+ -type regions 8a and 8b are selectively formed by solid-phase diffusion of boron.
As shown in FIG. 2E, after the third silicon oxide film 7 is removed, an n-type layer 9 is epitaxially grown.
Subsequently, as shown in FIG. 2F, an n-type well region is formed on the n.sup.+ -type region 6a. A p-channel MOS transistor Q.sub.1 is formed in the n-type well region. A p-type well region is formed on the p.sup.+ -type region 8a. An n-channel MOS transistor Q.sub.2 is formed in the p-type well region. An npn transistor Q.sub.3 is then formed on an n-type layer 9 in the n.sup.+ -type region 6b.
In a Bi-CMOS integrated circuit using a p-type silicon substrate and an n-type epitaxial layer, the following requirements must be satisfied: a reduction in collector resistance of an npn transistor; connection between the p-type silicon substrate and a p-type well in which an n-channel MOS transistor is formed; and an increase in impurity concentration in the n.sup.+ -type regions 6a and 6b and p.sup.+ -type regions 8a and 8b.
When such a circuit is formed by the above-described conventional manufacturing method, the gap between an opening, used to form a diffusion source of an n.sup.+ -type region, and an opening, used to form a diffusion source of a p.sup.+ -type region, is as small as about the width of the third silicon oxide film formed under the silicon nitride film 3 during selective oxidation of silicon.
For this reason, as indicated by dotted lines in FIG. 2F, since the n.sup.+ -type and p.sup.+ -type regions directly overlap each other at their boundary regions, a decrease in reverse breakdown voltage between n.sup.+ -type regions tend to occur in addition to an increase in capacitance. Therefore, an increase in operation speed of an npn transistor, achieved by increasing the impurity concentration of n.sup.+ -type regions, has limitations. In addition, such a conventional technique cannot be suitably applied to a Bi-CMOS integrated circuit to be operated with a high power source voltage.